RXFFR=Val_0x0
Receiver Block FIFO Reset Register
RXFFR | Receiver FIFO Reset. Writing a 0x1 to this bit flushes all the RX FIFOs (this is a self clearing bit). The Receiver block must be disabled before writing to this bit. 0 (Val_0x0): Does not flush the RX FIFO 1 (Val_0x1): Flushes the RX FIFO |